2014-06-02 02:33:21 -07:00
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/*
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* Author: Yevgeniy Kiveisha <yevgeniy.kiveisha@intel.com>
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* Copyright (c) 2014 Intel Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <iostream>
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#include <unistd.h>
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2014-06-03 09:35:47 +00:00
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#include <stdlib.h>
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2014-06-02 02:33:21 -07:00
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#include "nrf24l01.h"
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using namespace upm;
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NRF24l01::NRF24l01 (uint8_t cs) {
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maa_init();
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nrfInitModule (cs, 8);
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}
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NRF24l01::~NRF24l01 () {
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maa_result_t error = MAA_SUCCESS;
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error = maa_spi_stop(m_spi);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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error = maa_gpio_close (m_cePinCtx);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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error = maa_gpio_close (m_csnPinCtx);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfInitModule (uint8_t chip_select, uint8_t chip_enable) {
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maa_result_t error = MAA_SUCCESS;
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m_csn = chip_select;
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m_ce = chip_enable;
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m_channel = 1;
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m_csnPinCtx = maa_gpio_init (m_csn);
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if (m_csnPinCtx == NULL) {
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fprintf (stderr, "Are you sure that pin%d you requested is valid on your platform?", m_csn);
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exit (1);
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}
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m_cePinCtx = maa_gpio_init (m_ce);
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if (m_cePinCtx == NULL) {
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fprintf (stderr, "Are you sure that pin%d you requested is valid on your platform?", m_ce);
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exit (1);
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}
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error = maa_gpio_dir (m_csnPinCtx, MAA_GPIO_OUT);
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if (error != MAA_SUCCESS) {
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maa_result_print (error);
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}
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error = maa_gpio_dir (m_cePinCtx, MAA_GPIO_OUT);
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if (error != MAA_SUCCESS) {
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maa_result_print (error);
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}
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nrfCELow ();
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m_spi = maa_spi_init (0);
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfConfigModule() {
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/* Set RF channel */
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nrfConfigRegister (RF_CH, m_channel);
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/* Set length of incoming payload */
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nrfConfigRegister (RX_PW_P0, m_payload);
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nrfConfigRegister (RX_PW_P1, m_payload);
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/* Set length of incoming payload for broadcast */
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nrfConfigRegister (RX_PW_P2, m_payload);
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/* Start receiver */
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nrfPowerUpRX ();
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nrfFlushRX ();
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}
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/* Clocks only one byte into the given MiRF register */
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfConfigRegister(uint8_t reg, uint8_t value) {
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nrfCSOn ();
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maa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
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maa_spi_write (m_spi, value);
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nrfCSOff ();
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfPowerUpRX() {
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m_ptx = 0;
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nrfCELow();
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nrfConfigRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
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nrfCEHigh();
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2014-06-02 11:49:57 +01:00
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nrfConfigRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
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2014-06-02 02:33:21 -07:00
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfFlushRX() {
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nrfCSOn ();
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maa_spi_write (m_spi, FLUSH_RX);
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nrfCSOff ();
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}
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/* Sets the receiving address */
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfSetRXaddr(uint8_t * addr) {
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nrfCELow();
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nrfWriteRegister(RX_ADDR_P1, addr, mirf_ADDR_LEN);
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nrfCEHigh();
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}
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/* Sets the transmitting address */
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfSetTXaddr(uint8_t * addr)
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{
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/* RX_ADDR_P0 must be set to the sending addr for auto ack to work. */
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nrfWriteRegister (RX_ADDR_P0, addr, mirf_ADDR_LEN);
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nrfWriteRegister (TX_ADDR, addr, mirf_ADDR_LEN);
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}
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/* The broadcast address should be 0xFFFFF */
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfSetBroadcastAddr (uint8_t * addr) {
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nrfCELow ();
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nrfWriteRegister (RX_ADDR_P2, addr, mirf_ADDR_LEN);
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nrfCEHigh ();
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfSetPayload (uint8_t load) {
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m_payload = load;
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}
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2014-06-02 11:49:57 +01:00
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void
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NRF24l01::nrfWriteRegister(uint8_t reg, uint8_t * value, uint8_t len)
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2014-06-02 02:33:21 -07:00
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{
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nrfCSOn ();
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maa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
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nrfTransmitSync(value, len);
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nrfCSOff ();
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfTransmitSync(uint8_t *dataout, uint8_t len){
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uint8_t i;
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for(i = 0; i < len; i++) {
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maa_spi_write (m_spi, dataout[i]);
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}
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}
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/* Checks if data is available for reading */
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2014-06-02 11:49:57 +01:00
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bool
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfDataReady() {
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uint8_t status = nrfGetStatus();
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if ( status & (1 << RX_DR) ) {
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return 1;
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}
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return !nrfRXFifoEmpty();
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}
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2014-06-02 11:49:57 +01:00
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uint8_t
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfGetStatus () {
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uint8_t rv;
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nrfReadRegister (STATUS, &rv, 1);
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return rv;
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}
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/* Reads an array of bytes from the given start position in the MiRF registers. */
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len)
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{
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nrfCSOn ();
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maa_spi_write (m_spi, R_REGISTER | (REGISTER_MASK & reg));
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nrfTransferSync (value, value, len);
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nrfCSOff ();
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfTransferSync (uint8_t *dataout,uint8_t *datain,uint8_t len) {
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uint8_t i;
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for(i = 0;i < len;i++) {
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datain[i] = maa_spi_write (m_spi, dataout[i]);
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}
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}
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2014-06-02 11:49:57 +01:00
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bool
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfRXFifoEmpty () {
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uint8_t fifo_status;
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nrfReadRegister (FIFO_STATUS, &fifo_status, sizeof(fifo_status));
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return (fifo_status & (1 << RX_EMPTY));
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}
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/* Reads payload bytes into data array */
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2014-06-02 11:49:57 +01:00
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void
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NRF24l01::nrfGetData (uint8_t * data)
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2014-06-02 02:33:21 -07:00
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{
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nrfCSOn ();
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/* Send cmd to read rx payload */
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maa_spi_write (m_spi, R_RX_PAYLOAD);
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/* Read payload */
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nrfTransferSync(data, data, m_payload);
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nrfCSOff ();
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nrfConfigRegister(STATUS, (1<<RX_DR));
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}
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/* Sends a data package to the default address. Be sure to send the correct
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* amount of bytes as configured as payload on the receiver. */
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfSend(uint8_t * value) {
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uint8_t status;
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status = nrfGetStatus();
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while (m_ptx) {
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status = nrfGetStatus();
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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m_ptx = 0;
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break;
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}
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} // Wait until last paket is send
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nrfCELow();
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nrfPowerUpTX(); // Set to transmitter mode , Power up
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nrfCSOn ();
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maa_spi_write (m_spi, FLUSH_TX); // Write cmd to flush tx fifo
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, W_TX_PAYLOAD); // Write cmd to write payload
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nrfTransmitSync(value, m_payload); // Write payload
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nrfCSOff ();
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nrfCEHigh(); // Start transmission
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfSend () {
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nrfSend (m_txBuffer);
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}
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2014-06-02 11:49:57 +01:00
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bool
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfIsSending () {
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uint8_t status;
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if (m_ptx) { // Sending mode.
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status = nrfGetStatus();
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/* if sending successful (TX_DS) or max retries exceded (MAX_RT). */
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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nrfPowerUpRX();
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2014-06-02 11:49:57 +01:00
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return false;
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2014-06-02 02:33:21 -07:00
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}
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return true;
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}
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return false;
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfPowerUpTX () {
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m_ptx = 1;
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nrfConfigRegister (CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfPowerDown () {
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nrfCELow ();
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nrfConfigRegister (CONFIG, mirf_CONFIG);
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}
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2014-06-02 11:49:57 +01:00
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maa_result_t
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfCEHigh () {
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return maa_gpio_write (m_cePinCtx, HIGH);
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}
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2014-06-02 11:49:57 +01:00
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maa_result_t
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfCELow () {
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return maa_gpio_write (m_cePinCtx, LOW);
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}
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2014-06-02 11:49:57 +01:00
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maa_result_t
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfCSOn () {
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return maa_gpio_write (m_csnPinCtx, LOW);
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}
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2014-06-02 11:49:57 +01:00
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maa_result_t
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfCSOff () {
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return maa_gpio_write (m_csnPinCtx, HIGH);
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}
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2014-06-02 11:49:57 +01:00
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void
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2014-06-02 02:33:21 -07:00
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NRF24l01::nrfListenForChannel() {
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if(!nrfIsSending() && nrfDataReady()) {
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nrfGetData(m_rxBuffer);
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dataRecievedHandler(); /* let know that data arrived */
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}
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}
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