mirror of
https://github.com/eclipse/upm.git
synced 2025-07-03 02:11:15 +03:00
styling: convert TAB to four SPACES
Signed-off-by: Kiveisha Yevgeniy <yevgeniy.kiveisha@intel.com>
This commit is contained in:
Kiveisha Yevgeniy
@ -31,21 +31,21 @@
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using namespace upm;
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NRF24l01::NRF24l01 (uint8_t cs) {
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maa_init();
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nrfInitModule (cs, 8);
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maa_init();
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nrfInitModule (cs, 8);
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}
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NRF24l01::~NRF24l01 () {
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maa_result_t error = MAA_SUCCESS;
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error = maa_spi_stop(m_spi);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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error = maa_gpio_close (m_cePinCtx);
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maa_result_t error = MAA_SUCCESS;
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error = maa_spi_stop(m_spi);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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error = maa_gpio_close (m_csnPinCtx);
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error = maa_gpio_close (m_cePinCtx);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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error = maa_gpio_close (m_csnPinCtx);
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if (error != MAA_SUCCESS) {
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maa_result_print(error);
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}
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@ -53,268 +53,268 @@ NRF24l01::~NRF24l01 () {
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void
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NRF24l01::nrfInitModule (uint8_t chip_select, uint8_t chip_enable) {
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maa_result_t error = MAA_SUCCESS;
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maa_result_t error = MAA_SUCCESS;
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m_csn = chip_select;
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m_ce = chip_enable;
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m_channel = 1;
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m_csn = chip_select;
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m_ce = chip_enable;
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m_channel = 1;
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m_csnPinCtx = maa_gpio_init (m_csn);
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if (m_csnPinCtx == NULL) {
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m_csnPinCtx = maa_gpio_init (m_csn);
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if (m_csnPinCtx == NULL) {
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fprintf (stderr, "Are you sure that pin%d you requested is valid on your platform?", m_csn);
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exit (1);
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}
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m_cePinCtx = maa_gpio_init (m_ce);
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if (m_cePinCtx == NULL) {
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exit (1);
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}
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m_cePinCtx = maa_gpio_init (m_ce);
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if (m_cePinCtx == NULL) {
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fprintf (stderr, "Are you sure that pin%d you requested is valid on your platform?", m_ce);
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exit (1);
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}
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error = maa_gpio_dir (m_csnPinCtx, MAA_GPIO_OUT);
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exit (1);
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}
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error = maa_gpio_dir (m_csnPinCtx, MAA_GPIO_OUT);
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if (error != MAA_SUCCESS) {
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maa_result_print (error);
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}
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error = maa_gpio_dir (m_cePinCtx, MAA_GPIO_OUT);
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error = maa_gpio_dir (m_cePinCtx, MAA_GPIO_OUT);
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if (error != MAA_SUCCESS) {
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maa_result_print (error);
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}
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nrfCELow ();
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m_spi = maa_spi_init (0);
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nrfCELow ();
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m_spi = maa_spi_init (0);
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}
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void
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NRF24l01::nrfConfigModule() {
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/* Set RF channel */
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nrfConfigRegister (RF_CH, m_channel);
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/* Set RF channel */
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nrfConfigRegister (RF_CH, m_channel);
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/* Set length of incoming payload */
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nrfConfigRegister (RX_PW_P0, m_payload);
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nrfConfigRegister (RX_PW_P1, m_payload);
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/* Set length of incoming payload for broadcast */
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nrfConfigRegister (RX_PW_P2, m_payload);
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/* Start receiver */
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nrfPowerUpRX ();
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nrfFlushRX ();
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/* Set length of incoming payload */
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nrfConfigRegister (RX_PW_P0, m_payload);
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nrfConfigRegister (RX_PW_P1, m_payload);
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/* Set length of incoming payload for broadcast */
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nrfConfigRegister (RX_PW_P2, m_payload);
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/* Start receiver */
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nrfPowerUpRX ();
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nrfFlushRX ();
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}
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/* Clocks only one byte into the given MiRF register */
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void
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NRF24l01::nrfConfigRegister(uint8_t reg, uint8_t value) {
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nrfCSOn ();
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maa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
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maa_spi_write (m_spi, value);
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
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maa_spi_write (m_spi, value);
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nrfCSOff ();
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}
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void
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NRF24l01::nrfPowerUpRX() {
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m_ptx = 0;
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nrfCELow();
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nrfConfigRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
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nrfCEHigh();
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nrfConfigRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
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m_ptx = 0;
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nrfCELow();
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nrfConfigRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
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nrfCEHigh();
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nrfConfigRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
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}
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void
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NRF24l01::nrfFlushRX() {
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nrfCSOn ();
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maa_spi_write (m_spi, FLUSH_RX);
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, FLUSH_RX);
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nrfCSOff ();
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}
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/* Sets the receiving address */
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void
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NRF24l01::nrfSetRXaddr(uint8_t * addr) {
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nrfCELow();
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nrfWriteRegister(RX_ADDR_P1, addr, mirf_ADDR_LEN);
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nrfCEHigh();
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nrfCELow();
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nrfWriteRegister(RX_ADDR_P1, addr, mirf_ADDR_LEN);
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nrfCEHigh();
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}
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/* Sets the transmitting address */
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void
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NRF24l01::nrfSetTXaddr(uint8_t * addr)
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{
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/* RX_ADDR_P0 must be set to the sending addr for auto ack to work. */
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nrfWriteRegister (RX_ADDR_P0, addr, mirf_ADDR_LEN);
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nrfWriteRegister (TX_ADDR, addr, mirf_ADDR_LEN);
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/* RX_ADDR_P0 must be set to the sending addr for auto ack to work. */
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nrfWriteRegister (RX_ADDR_P0, addr, mirf_ADDR_LEN);
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nrfWriteRegister (TX_ADDR, addr, mirf_ADDR_LEN);
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}
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/* The broadcast address should be 0xFFFFF */
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void
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NRF24l01::nrfSetBroadcastAddr (uint8_t * addr) {
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nrfCELow ();
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nrfWriteRegister (RX_ADDR_P2, addr, mirf_ADDR_LEN);
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nrfCEHigh ();
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nrfCELow ();
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nrfWriteRegister (RX_ADDR_P2, addr, mirf_ADDR_LEN);
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nrfCEHigh ();
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}
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void
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NRF24l01::nrfSetPayload (uint8_t load) {
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m_payload = load;
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m_payload = load;
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}
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void
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NRF24l01::nrfWriteRegister(uint8_t reg, uint8_t * value, uint8_t len)
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{
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nrfCSOn ();
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maa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
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nrfTransmitSync(value, len);
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
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nrfTransmitSync(value, len);
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nrfCSOff ();
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}
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void
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NRF24l01::nrfTransmitSync(uint8_t *dataout, uint8_t len){
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uint8_t i;
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for(i = 0; i < len; i++) {
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maa_spi_write (m_spi, dataout[i]);
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}
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uint8_t i;
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for(i = 0; i < len; i++) {
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maa_spi_write (m_spi, dataout[i]);
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}
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}
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/* Checks if data is available for reading */
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bool
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NRF24l01::nrfDataReady() {
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uint8_t status = nrfGetStatus();
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if ( status & (1 << RX_DR) ) {
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return 1;
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}
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return !nrfRXFifoEmpty();
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uint8_t status = nrfGetStatus();
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if ( status & (1 << RX_DR) ) {
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return 1;
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}
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return !nrfRXFifoEmpty();
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}
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uint8_t
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NRF24l01::nrfGetStatus () {
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uint8_t rv;
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nrfReadRegister (STATUS, &rv, 1);
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return rv;
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uint8_t rv;
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nrfReadRegister (STATUS, &rv, 1);
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return rv;
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}
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/* Reads an array of bytes from the given start position in the MiRF registers. */
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void
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NRF24l01::nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len)
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{
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nrfCSOn ();
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maa_spi_write (m_spi, R_REGISTER | (REGISTER_MASK & reg));
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nrfTransferSync (value, value, len);
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, R_REGISTER | (REGISTER_MASK & reg));
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nrfTransferSync (value, value, len);
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nrfCSOff ();
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}
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void
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NRF24l01::nrfTransferSync (uint8_t *dataout,uint8_t *datain,uint8_t len) {
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uint8_t i;
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for(i = 0;i < len;i++) {
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datain[i] = maa_spi_write (m_spi, dataout[i]);
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}
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uint8_t i;
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for(i = 0;i < len;i++) {
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datain[i] = maa_spi_write (m_spi, dataout[i]);
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}
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}
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bool
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NRF24l01::nrfRXFifoEmpty () {
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uint8_t fifo_status;
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nrfReadRegister (FIFO_STATUS, &fifo_status, sizeof(fifo_status));
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return (fifo_status & (1 << RX_EMPTY));
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uint8_t fifo_status;
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nrfReadRegister (FIFO_STATUS, &fifo_status, sizeof(fifo_status));
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return (fifo_status & (1 << RX_EMPTY));
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}
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/* Reads payload bytes into data array */
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void
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NRF24l01::nrfGetData (uint8_t * data)
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{
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nrfCSOn ();
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/* Send cmd to read rx payload */
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maa_spi_write (m_spi, R_RX_PAYLOAD);
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/* Read payload */
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nrfTransferSync(data, data, m_payload);
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nrfCSOff ();
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nrfConfigRegister(STATUS, (1<<RX_DR));
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nrfCSOn ();
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/* Send cmd to read rx payload */
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maa_spi_write (m_spi, R_RX_PAYLOAD);
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/* Read payload */
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nrfTransferSync(data, data, m_payload);
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nrfCSOff ();
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nrfConfigRegister(STATUS, (1<<RX_DR));
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}
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/* Sends a data package to the default address. Be sure to send the correct
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* amount of bytes as configured as payload on the receiver. */
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void
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NRF24l01::nrfSend(uint8_t * value) {
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uint8_t status;
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status = nrfGetStatus();
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uint8_t status;
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status = nrfGetStatus();
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while (m_ptx) {
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status = nrfGetStatus();
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while (m_ptx) {
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status = nrfGetStatus();
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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m_ptx = 0;
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break;
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}
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} // Wait until last paket is send
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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m_ptx = 0;
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break;
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}
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} // Wait until last paket is send
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nrfCELow();
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nrfPowerUpTX(); // Set to transmitter mode , Power up
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nrfCSOn ();
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maa_spi_write (m_spi, FLUSH_TX); // Write cmd to flush tx fifo
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, W_TX_PAYLOAD); // Write cmd to write payload
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nrfTransmitSync(value, m_payload); // Write payload
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nrfCSOff ();
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nrfCEHigh(); // Start transmission
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nrfCELow();
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nrfPowerUpTX(); // Set to transmitter mode , Power up
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nrfCSOn ();
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maa_spi_write (m_spi, FLUSH_TX); // Write cmd to flush tx fifo
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nrfCSOff ();
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nrfCSOn ();
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maa_spi_write (m_spi, W_TX_PAYLOAD); // Write cmd to write payload
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nrfTransmitSync(value, m_payload); // Write payload
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nrfCSOff ();
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nrfCEHigh(); // Start transmission
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}
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void
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NRF24l01::nrfSend () {
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nrfSend (m_txBuffer);
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nrfSend (m_txBuffer);
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}
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bool
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NRF24l01::nrfIsSending () {
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uint8_t status;
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if (m_ptx) { // Sending mode.
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status = nrfGetStatus();
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/* if sending successful (TX_DS) or max retries exceded (MAX_RT). */
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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nrfPowerUpRX();
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return false;
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}
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return true;
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}
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return false;
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uint8_t status;
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if (m_ptx) { // Sending mode.
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status = nrfGetStatus();
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/* if sending successful (TX_DS) or max retries exceded (MAX_RT). */
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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nrfPowerUpRX();
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return false;
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}
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return true;
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}
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return false;
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}
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void
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NRF24l01::nrfPowerUpTX () {
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m_ptx = 1;
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nrfConfigRegister (CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
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m_ptx = 1;
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nrfConfigRegister (CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
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}
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void
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NRF24l01::nrfPowerDown () {
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nrfCELow ();
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nrfConfigRegister (CONFIG, mirf_CONFIG);
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nrfCELow ();
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nrfConfigRegister (CONFIG, mirf_CONFIG);
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}
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maa_result_t
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NRF24l01::nrfCEHigh () {
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return maa_gpio_write (m_cePinCtx, HIGH);
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return maa_gpio_write (m_cePinCtx, HIGH);
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}
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maa_result_t
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NRF24l01::nrfCELow () {
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return maa_gpio_write (m_cePinCtx, LOW);
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return maa_gpio_write (m_cePinCtx, LOW);
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}
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maa_result_t
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NRF24l01::nrfCSOn () {
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return maa_gpio_write (m_csnPinCtx, LOW);
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return maa_gpio_write (m_csnPinCtx, LOW);
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}
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maa_result_t
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NRF24l01::nrfCSOff () {
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return maa_gpio_write (m_csnPinCtx, HIGH);
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return maa_gpio_write (m_csnPinCtx, HIGH);
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}
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void
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NRF24l01::nrfListenForChannel() {
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if(!nrfIsSending() && nrfDataReady()) {
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nrfGetData(m_rxBuffer);
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dataRecievedHandler(); /* let know that data arrived */
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}
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if(!nrfIsSending() && nrfDataReady()) {
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nrfGetData(m_rxBuffer);
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dataRecievedHandler(); /* let know that data arrived */
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}
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}
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@ -29,90 +29,90 @@
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#include <maa/spi.h>
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/* Memory Map */
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#define CONFIG 0x00
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#define EN_AA 0x01
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#define EN_RXADDR 0x02
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#define SETUP_AW 0x03
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#define SETUP_RETR 0x04
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#define RF_CH 0x05
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#define RF_SETUP 0x06
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#define STATUS 0x07
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#define OBSERVE_TX 0x08
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#define CD 0x09
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#define RX_ADDR_P0 0x0A
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#define RX_ADDR_P1 0x0B
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#define RX_ADDR_P2 0x0C
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#define RX_ADDR_P3 0x0D
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#define RX_ADDR_P4 0x0E
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#define RX_ADDR_P5 0x0F
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#define TX_ADDR 0x10
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#define RX_PW_P0 0x11
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#define RX_PW_P1 0x12
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#define RX_PW_P2 0x13
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#define RX_PW_P3 0x14
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#define RX_PW_P4 0x15
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#define RX_PW_P5 0x16
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#define FIFO_STATUS 0x17
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#define CONFIG 0x00
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#define EN_AA 0x01
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#define EN_RXADDR 0x02
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#define SETUP_AW 0x03
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||||
#define SETUP_RETR 0x04
|
||||
#define RF_CH 0x05
|
||||
#define RF_SETUP 0x06
|
||||
#define STATUS 0x07
|
||||
#define OBSERVE_TX 0x08
|
||||
#define CD 0x09
|
||||
#define RX_ADDR_P0 0x0A
|
||||
#define RX_ADDR_P1 0x0B
|
||||
#define RX_ADDR_P2 0x0C
|
||||
#define RX_ADDR_P3 0x0D
|
||||
#define RX_ADDR_P4 0x0E
|
||||
#define RX_ADDR_P5 0x0F
|
||||
#define TX_ADDR 0x10
|
||||
#define RX_PW_P0 0x11
|
||||
#define RX_PW_P1 0x12
|
||||
#define RX_PW_P2 0x13
|
||||
#define RX_PW_P3 0x14
|
||||
#define RX_PW_P4 0x15
|
||||
#define RX_PW_P5 0x16
|
||||
#define FIFO_STATUS 0x17
|
||||
|
||||
/* Bit Mnemonics */
|
||||
#define MASK_RX_DR 6
|
||||
#define MASK_TX_DS 5
|
||||
#define MASK_MAX_RT 4
|
||||
#define EN_CRC 3
|
||||
#define CRCO 2
|
||||
#define PWR_UP 1
|
||||
#define PRIM_RX 0
|
||||
#define ENAA_P5 5
|
||||
#define ENAA_P4 4
|
||||
#define ENAA_P3 3
|
||||
#define ENAA_P2 2
|
||||
#define ENAA_P1 1
|
||||
#define ENAA_P0 0
|
||||
#define ERX_P5 5
|
||||
#define ERX_P4 4
|
||||
#define ERX_P3 3
|
||||
#define ERX_P2 2
|
||||
#define ERX_P1 1
|
||||
#define ERX_P0 0
|
||||
#define AW 0
|
||||
#define ARD 4
|
||||
#define ARC 0
|
||||
#define PLL_LOCK 4
|
||||
#define RF_DR 3
|
||||
#define RF_PWR 1
|
||||
#define LNA_HCURR 0
|
||||
#define RX_DR 6
|
||||
#define TX_DS 5
|
||||
#define MAX_RT 4
|
||||
#define RX_P_NO 1
|
||||
#define TX_FULL 0
|
||||
#define PLOS_CNT 4
|
||||
#define ARC_CNT 0
|
||||
#define TX_REUSE 6
|
||||
#define FIFO_FULL 5
|
||||
#define TX_EMPTY 4
|
||||
#define RX_FULL 1
|
||||
#define RX_EMPTY 0
|
||||
#define MASK_RX_DR 6
|
||||
#define MASK_TX_DS 5
|
||||
#define MASK_MAX_RT 4
|
||||
#define EN_CRC 3
|
||||
#define CRCO 2
|
||||
#define PWR_UP 1
|
||||
#define PRIM_RX 0
|
||||
#define ENAA_P5 5
|
||||
#define ENAA_P4 4
|
||||
#define ENAA_P3 3
|
||||
#define ENAA_P2 2
|
||||
#define ENAA_P1 1
|
||||
#define ENAA_P0 0
|
||||
#define ERX_P5 5
|
||||
#define ERX_P4 4
|
||||
#define ERX_P3 3
|
||||
#define ERX_P2 2
|
||||
#define ERX_P1 1
|
||||
#define ERX_P0 0
|
||||
#define AW 0
|
||||
#define ARD 4
|
||||
#define ARC 0
|
||||
#define PLL_LOCK 4
|
||||
#define RF_DR 3
|
||||
#define RF_PWR 1
|
||||
#define LNA_HCURR 0
|
||||
#define RX_DR 6
|
||||
#define TX_DS 5
|
||||
#define MAX_RT 4
|
||||
#define RX_P_NO 1
|
||||
#define TX_FULL 0
|
||||
#define PLOS_CNT 4
|
||||
#define ARC_CNT 0
|
||||
#define TX_REUSE 6
|
||||
#define FIFO_FULL 5
|
||||
#define TX_EMPTY 4
|
||||
#define RX_FULL 1
|
||||
#define RX_EMPTY 0
|
||||
|
||||
/* Instruction Mnemonics */
|
||||
#define R_REGISTER 0x00
|
||||
#define W_REGISTER 0x20
|
||||
#define REGISTER_MASK 0x1F
|
||||
#define R_RX_PAYLOAD 0x61
|
||||
#define W_TX_PAYLOAD 0xA0
|
||||
#define FLUSH_TX 0xE1
|
||||
#define FLUSH_RX 0xE2
|
||||
#define REUSE_TX_PL 0xE3
|
||||
#define NOP 0xFF
|
||||
#define R_REGISTER 0x00
|
||||
#define W_REGISTER 0x20
|
||||
#define REGISTER_MASK 0x1F
|
||||
#define R_RX_PAYLOAD 0x61
|
||||
#define W_TX_PAYLOAD 0xA0
|
||||
#define FLUSH_TX 0xE1
|
||||
#define FLUSH_RX 0xE2
|
||||
#define REUSE_TX_PL 0xE3
|
||||
#define NOP 0xFF
|
||||
|
||||
/* Nrf24l settings */
|
||||
#define mirf_ADDR_LEN 5
|
||||
#define mirf_CONFIG ((1<<EN_CRC) | (0<<CRCO) )
|
||||
#define mirf_ADDR_LEN 5
|
||||
#define mirf_CONFIG ((1<<EN_CRC) | (0<<CRCO) )
|
||||
|
||||
#define MAX_BUFFER 32
|
||||
#define MAX_BUFFER 32
|
||||
|
||||
#define HIGH 1
|
||||
#define LOW 0
|
||||
#define HIGH 1
|
||||
#define LOW 0
|
||||
|
||||
namespace upm {
|
||||
|
||||
@ -120,61 +120,61 @@ typedef void (* funcPtrVoidVoid) ();
|
||||
|
||||
class NRF24l01 {
|
||||
public:
|
||||
NRF24l01 (uint8_t cs);
|
||||
~NRF24l01 ();
|
||||
std::string name()
|
||||
NRF24l01 (uint8_t cs);
|
||||
~NRF24l01 ();
|
||||
std::string name()
|
||||
{
|
||||
return m_name;
|
||||
}
|
||||
|
||||
void nrfInitModule (uint8_t chipSelect, uint8_t chipEnable);
|
||||
void nrfConfigModule ();
|
||||
void nrfSend (uint8_t *value);
|
||||
void nrfSend ();
|
||||
void nrfSetRXaddr (uint8_t * addr);
|
||||
void nrfSetTXaddr (uint8_t * addr);
|
||||
void nrfSetBroadcastAddr (uint8_t * addr);
|
||||
void nrfSetPayload (uint8_t load);
|
||||
bool nrfDataReady ();
|
||||
bool nrfIsSending ();
|
||||
bool nrfRXFifoEmpty ();
|
||||
bool nrfTXFifoEmpty ();
|
||||
void nrfGetData (uint8_t * data);
|
||||
uint8_t nrfGetStatus ();
|
||||
|
||||
void nrfTransmitSync (uint8_t *dataout, uint8_t len);
|
||||
void nrfTransferSync (uint8_t *dataout ,uint8_t *datain, uint8_t len);
|
||||
void nrfConfigRegister (uint8_t reg, uint8_t value);
|
||||
void nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len);
|
||||
void nrfWriteRegister (uint8_t reg, uint8_t * value, uint8_t len);
|
||||
void nrfPowerUpRX ();
|
||||
void nrfPowerUpTX ();
|
||||
void nrfPowerDown ();
|
||||
void nrfInitModule (uint8_t chipSelect, uint8_t chipEnable);
|
||||
void nrfConfigModule ();
|
||||
void nrfSend (uint8_t *value);
|
||||
void nrfSend ();
|
||||
void nrfSetRXaddr (uint8_t * addr);
|
||||
void nrfSetTXaddr (uint8_t * addr);
|
||||
void nrfSetBroadcastAddr (uint8_t * addr);
|
||||
void nrfSetPayload (uint8_t load);
|
||||
bool nrfDataReady ();
|
||||
bool nrfIsSending ();
|
||||
bool nrfRXFifoEmpty ();
|
||||
bool nrfTXFifoEmpty ();
|
||||
void nrfGetData (uint8_t * data);
|
||||
uint8_t nrfGetStatus ();
|
||||
|
||||
void nrfTransmitSync (uint8_t *dataout, uint8_t len);
|
||||
void nrfTransferSync (uint8_t *dataout ,uint8_t *datain, uint8_t len);
|
||||
void nrfConfigRegister (uint8_t reg, uint8_t value);
|
||||
void nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len);
|
||||
void nrfWriteRegister (uint8_t reg, uint8_t * value, uint8_t len);
|
||||
void nrfPowerUpRX ();
|
||||
void nrfPowerUpTX ();
|
||||
void nrfPowerDown ();
|
||||
|
||||
maa_result_t nrfCEHigh ();
|
||||
maa_result_t nrfCELow ();
|
||||
maa_result_t nrfCSOn ();
|
||||
maa_result_t nrfCSOff ();
|
||||
void nrfFlushRX ();
|
||||
void nrfListenForChannel();
|
||||
maa_result_t nrfCEHigh ();
|
||||
maa_result_t nrfCELow ();
|
||||
maa_result_t nrfCSOn ();
|
||||
maa_result_t nrfCSOff ();
|
||||
void nrfFlushRX ();
|
||||
void nrfListenForChannel();
|
||||
|
||||
uint8_t m_rxBuffer[MAX_BUFFER];
|
||||
uint8_t m_txBuffer[MAX_BUFFER];
|
||||
uint8_t m_rxBuffer[MAX_BUFFER];
|
||||
uint8_t m_txBuffer[MAX_BUFFER];
|
||||
|
||||
funcPtrVoidVoid dataRecievedHandler;
|
||||
private:
|
||||
maa_spi_context m_spi;
|
||||
uint8_t m_ce;
|
||||
uint8_t m_csn;
|
||||
uint8_t m_channel;
|
||||
uint8_t m_ptx;
|
||||
uint8_t m_payload;
|
||||
uint8_t m_localAddress[5];
|
||||
|
||||
maa_gpio_context m_csnPinCtx;
|
||||
maa_gpio_context m_cePinCtx;
|
||||
funcPtrVoidVoid dataRecievedHandler;
|
||||
private:
|
||||
maa_spi_context m_spi;
|
||||
uint8_t m_ce;
|
||||
uint8_t m_csn;
|
||||
uint8_t m_channel;
|
||||
uint8_t m_ptx;
|
||||
uint8_t m_payload;
|
||||
uint8_t m_localAddress[5];
|
||||
|
||||
maa_gpio_context m_csnPinCtx;
|
||||
maa_gpio_context m_cePinCtx;
|
||||
|
||||
std::string m_name;
|
||||
std::string m_name;
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user