mirror of
https://github.com/eclipse/upm.git
synced 2025-12-15 13:26:07 +03:00
nrf24l01: added new feature BLE broadcasting with example and new methods to nrf24l01 (setChannel, setPower, etc... )
Signed-off-by: Kiveisha Yevgeniy <yevgeniy.kiveisha@intel.com>
This commit is contained in:
Kiveisha Yevgeniy
@@ -1,6 +1,7 @@
|
||||
/*
|
||||
* Author: Yevgeniy Kiveisha <yevgeniy.kiveisha@intel.com>
|
||||
* Copyright (c) 2014 Intel Corporation.
|
||||
* BLE Beaconing based on http://dmitry.gr/index.php?r=05.Projects&proj=11.%20Bluetooth%20LE%20fakery
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
@@ -30,12 +31,12 @@
|
||||
|
||||
using namespace upm;
|
||||
|
||||
NRF24l01::NRF24l01 (uint8_t cs) {
|
||||
NRF24L01::NRF24L01 (uint8_t cs, uint8_t ce) {
|
||||
mraa_init();
|
||||
nrfInitModule (cs, 8);
|
||||
init (cs, ce);
|
||||
}
|
||||
|
||||
NRF24l01::~NRF24l01 () {
|
||||
NRF24L01::~NRF24L01 () {
|
||||
mraa_result_t error = MRAA_SUCCESS;
|
||||
error = mraa_spi_stop(m_spi);
|
||||
if (error != MRAA_SUCCESS) {
|
||||
@@ -52,12 +53,12 @@ NRF24l01::~NRF24l01 () {
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfInitModule (uint8_t chip_select, uint8_t chip_enable) {
|
||||
NRF24L01::init (uint8_t chip_select, uint8_t chip_enable) {
|
||||
mraa_result_t error = MRAA_SUCCESS;
|
||||
|
||||
m_csn = chip_select;
|
||||
m_ce = chip_enable;
|
||||
m_channel = 1;
|
||||
m_csn = chip_select;
|
||||
m_ce = chip_enable;
|
||||
m_channel = 99;
|
||||
|
||||
m_csnPinCtx = mraa_gpio_init (m_csn);
|
||||
if (m_csnPinCtx == NULL) {
|
||||
@@ -81,163 +82,35 @@ NRF24l01::nrfInitModule (uint8_t chip_select, uint8_t chip_enable) {
|
||||
mraa_result_print (error);
|
||||
}
|
||||
|
||||
nrfCELow ();
|
||||
ceLow();
|
||||
csOff ();
|
||||
|
||||
m_spi = mraa_spi_init (0);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfConfigModule() {
|
||||
NRF24L01::configure () {
|
||||
/* Set RF channel */
|
||||
nrfConfigRegister (RF_CH, m_channel);
|
||||
setRegister (RF_CH, m_channel);
|
||||
|
||||
/* Set length of incoming payload */
|
||||
nrfConfigRegister (RX_PW_P0, m_payload);
|
||||
nrfConfigRegister (RX_PW_P1, m_payload);
|
||||
setRegister (RX_PW_P0, m_payload);
|
||||
|
||||
/* Set length of incoming payload for broadcast */
|
||||
nrfConfigRegister (RX_PW_P2, m_payload);
|
||||
setRegister (RX_PW_P1, m_payload);
|
||||
|
||||
/* Start receiver */
|
||||
nrfPowerUpRX ();
|
||||
nrfFlushRX ();
|
||||
}
|
||||
|
||||
/* Clocks only one byte into the given MiRF register */
|
||||
void
|
||||
NRF24l01::nrfConfigRegister(uint8_t reg, uint8_t value) {
|
||||
nrfCSOn ();
|
||||
mraa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
|
||||
mraa_spi_write (m_spi, value);
|
||||
nrfCSOff ();
|
||||
rxPowerUp ();
|
||||
rxFlushBuffer ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfPowerUpRX() {
|
||||
m_ptx = 0;
|
||||
nrfCELow();
|
||||
nrfConfigRegister(CONFIG, NRF_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
|
||||
nrfCEHigh();
|
||||
nrfConfigRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfFlushRX() {
|
||||
nrfCSOn ();
|
||||
mraa_spi_write (m_spi, FLUSH_RX);
|
||||
nrfCSOff ();
|
||||
}
|
||||
|
||||
/* Sets the receiving address */
|
||||
void
|
||||
NRF24l01::nrfSetRXaddr(uint8_t * addr) {
|
||||
nrfCELow();
|
||||
nrfWriteRegister(RX_ADDR_P1, addr, ADDR_LEN);
|
||||
nrfCEHigh();
|
||||
}
|
||||
|
||||
/* Sets the transmitting address */
|
||||
void
|
||||
NRF24l01::nrfSetTXaddr(uint8_t * addr)
|
||||
{
|
||||
/* RX_ADDR_P0 must be set to the sending addr for auto ack to work. */
|
||||
nrfWriteRegister (RX_ADDR_P0, addr, ADDR_LEN);
|
||||
nrfWriteRegister (TX_ADDR, addr, ADDR_LEN);
|
||||
}
|
||||
|
||||
/* The broadcast address should be 0xFFFFF */
|
||||
void
|
||||
NRF24l01::nrfSetBroadcastAddr (uint8_t * addr) {
|
||||
nrfCELow ();
|
||||
nrfWriteRegister (RX_ADDR_P2, addr, ADDR_LEN);
|
||||
nrfCEHigh ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfSetPayload (uint8_t load) {
|
||||
m_payload = load;
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfWriteRegister(uint8_t reg, uint8_t * value, uint8_t len)
|
||||
{
|
||||
nrfCSOn ();
|
||||
mraa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
|
||||
nrfTransmitSync(value, len);
|
||||
nrfCSOff ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfTransmitSync(uint8_t *dataout, uint8_t len){
|
||||
uint8_t i;
|
||||
for(i = 0; i < len; i++) {
|
||||
mraa_spi_write (m_spi, dataout[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Checks if data is available for reading */
|
||||
bool
|
||||
NRF24l01::nrfDataReady() {
|
||||
uint8_t status = nrfGetStatus();
|
||||
if ( status & (1 << RX_DR) ) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return !nrfRXFifoEmpty();
|
||||
}
|
||||
|
||||
uint8_t
|
||||
NRF24l01::nrfGetStatus () {
|
||||
uint8_t rv;
|
||||
nrfReadRegister (STATUS, &rv, 1);
|
||||
return rv;
|
||||
}
|
||||
|
||||
/* Reads an array of bytes from the given start position in the MiRF registers. */
|
||||
void
|
||||
NRF24l01::nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len)
|
||||
{
|
||||
nrfCSOn ();
|
||||
mraa_spi_write (m_spi, R_REGISTER | (REGISTER_MASK & reg));
|
||||
nrfTransferSync (value, value, len);
|
||||
nrfCSOff ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfTransferSync (uint8_t *dataout,uint8_t *datain,uint8_t len) {
|
||||
uint8_t i;
|
||||
for(i = 0;i < len;i++) {
|
||||
datain[i] = mraa_spi_write (m_spi, dataout[i]);
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
NRF24l01::nrfRXFifoEmpty () {
|
||||
uint8_t fifo_status;
|
||||
nrfReadRegister (FIFO_STATUS, &fifo_status, sizeof(fifo_status));
|
||||
return (fifo_status & (1 << RX_EMPTY));
|
||||
}
|
||||
|
||||
/* Reads payload bytes into data array */
|
||||
void
|
||||
NRF24l01::nrfGetData (uint8_t * data)
|
||||
{
|
||||
nrfCSOn ();
|
||||
/* Send cmd to read rx payload */
|
||||
mraa_spi_write (m_spi, R_RX_PAYLOAD);
|
||||
/* Read payload */
|
||||
nrfTransferSync(data, data, m_payload);
|
||||
nrfCSOff ();
|
||||
nrfConfigRegister(STATUS, (1<<RX_DR));
|
||||
}
|
||||
|
||||
/* Sends a data package to the default address. Be sure to send the correct
|
||||
* amount of bytes as configured as payload on the receiver. */
|
||||
void
|
||||
NRF24l01::nrfSend(uint8_t * value) {
|
||||
NRF24L01::send (uint8_t * value) {
|
||||
uint8_t status;
|
||||
status = nrfGetStatus();
|
||||
status = getStatus();
|
||||
|
||||
while (m_ptx) {
|
||||
status = nrfGetStatus();
|
||||
status = getStatus();
|
||||
|
||||
if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
|
||||
m_ptx = 0;
|
||||
@@ -245,32 +118,69 @@ NRF24l01::nrfSend(uint8_t * value) {
|
||||
}
|
||||
} // Wait until last paket is send
|
||||
|
||||
nrfCELow();
|
||||
nrfPowerUpTX(); // Set to transmitter mode , Power up
|
||||
nrfCSOn ();
|
||||
mraa_spi_write (m_spi, FLUSH_TX); // Write cmd to flush tx fifo
|
||||
nrfCSOff ();
|
||||
ceLow ();
|
||||
txPowerUp (); // Set to transmitter mode , Power up
|
||||
txFlushBuffer ();
|
||||
|
||||
nrfCSOn ();
|
||||
mraa_spi_write (m_spi, W_TX_PAYLOAD); // Write cmd to write payload
|
||||
nrfTransmitSync(value, m_payload); // Write payload
|
||||
nrfCSOff ();
|
||||
nrfCEHigh(); // Start transmission
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, W_TX_PAYLOAD); // Write cmd to write payload
|
||||
writeBytes (value, NULL, m_payload); // Write payload
|
||||
csOff ();
|
||||
ceHigh(); // Start transmission
|
||||
|
||||
while (dataSending ()) { }
|
||||
|
||||
usleep (10000);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfSend () {
|
||||
nrfSend (m_txBuffer);
|
||||
NRF24L01::send () {
|
||||
send (m_txBuffer);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setSourceAddress (uint8_t * addr) {
|
||||
ceLow ();
|
||||
writeRegister (RX_ADDR_P0, addr, ADDR_LEN);
|
||||
ceHigh ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setDestinationAddress (uint8_t * addr) {
|
||||
writeRegister (TX_ADDR, addr, ADDR_LEN);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setBroadcastAddress (uint8_t * addr) {
|
||||
writeRegister (RX_ADDR_P1, addr, ADDR_LEN);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setPayload (uint8_t payload) {
|
||||
m_payload = payload;
|
||||
}
|
||||
|
||||
bool
|
||||
NRF24l01::nrfIsSending () {
|
||||
NRF24L01::dataReady () {
|
||||
/* See note in getData() function - just checking RX_DR isn't good enough */
|
||||
uint8_t status = getStatus();
|
||||
/* We can short circuit on RX_DR, but if it's not set, we still need
|
||||
* to check the FIFO for any pending packets */
|
||||
if ( status & (1 << RX_DR) ) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return !rxFifoEmpty();
|
||||
}
|
||||
|
||||
bool
|
||||
NRF24L01::dataSending () {
|
||||
uint8_t status;
|
||||
if (m_ptx) { // Sending mode.
|
||||
status = nrfGetStatus();
|
||||
if(m_ptx) { // Sending mode.
|
||||
status = getStatus();
|
||||
/* if sending successful (TX_DS) or max retries exceded (MAX_RT). */
|
||||
if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
|
||||
nrfPowerUpRX();
|
||||
rxPowerUp ();
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
@@ -279,41 +189,347 @@ NRF24l01::nrfIsSending () {
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfPowerUpTX () {
|
||||
m_ptx = 1;
|
||||
nrfConfigRegister (CONFIG, NRF_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
|
||||
NRF24L01::getData (uint8_t * data) {
|
||||
csOn ();
|
||||
/* Send cmd to read rx payload */
|
||||
mraa_spi_write (m_spi, R_RX_PAYLOAD);
|
||||
/* Read payload */
|
||||
writeBytes (data, data, m_payload);
|
||||
csOff ();
|
||||
/* NVI: per product spec, p 67, note c:
|
||||
* "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
|
||||
* for handling this interrupt should be: 1) read payload through SPI,
|
||||
* 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
|
||||
* payloads available in RX FIFO, 4) if there are more data in RX FIFO,
|
||||
* repeat from step 1)."
|
||||
* So if we're going to clear RX_DR here, we need to check the RX FIFO
|
||||
* in the dataReady() function */
|
||||
/* Reset status register */
|
||||
setRegister (STATUS, (1<<RX_DR));
|
||||
}
|
||||
|
||||
uint8_t
|
||||
NRF24L01::getStatus() {
|
||||
return getRegister (STATUS);
|
||||
}
|
||||
|
||||
bool
|
||||
NRF24L01::rxFifoEmpty () {
|
||||
uint8_t fifoStatus = getRegister (FIFO_STATUS);
|
||||
return (fifoStatus & (1 << RX_EMPTY));
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfPowerDown () {
|
||||
nrfCELow ();
|
||||
nrfConfigRegister (CONFIG, NRF_CONFIG);
|
||||
NRF24L01::rxPowerUp () {
|
||||
m_ptx = 0;
|
||||
ceLow ();
|
||||
setRegister (CONFIG, _CONFIG | ( (1 << PWR_UP) | (1 << PRIM_RX) ));
|
||||
ceHigh ();
|
||||
setRegister (STATUS, (1 << TX_DS) | (1 << MAX_RT));
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::rxFlushBuffer () {
|
||||
sendCommand (FLUSH_RX);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::txPowerUp () {
|
||||
m_ptx = 1;
|
||||
setRegister (CONFIG, _CONFIG | ( (1 << PWR_UP) | (0 << PRIM_RX) ));
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::powerDown(){
|
||||
ceLow ();
|
||||
setRegister (CONFIG, _CONFIG);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setChannel (uint8_t channel) {
|
||||
m_channel = channel;
|
||||
setRegister (RF_CH, channel);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setPower (power_t power) {
|
||||
uint8_t setupRegisterData = 0;
|
||||
|
||||
switch (power) {
|
||||
case NRF_0DBM:
|
||||
m_power = 3;
|
||||
break;
|
||||
case NRF_6DBM:
|
||||
m_power = 2;
|
||||
break;
|
||||
case NRF_12DBM:
|
||||
m_power = 1;
|
||||
break;
|
||||
case NRF_18DBM:
|
||||
m_power = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
setupRegisterData = getRegister (RF_SETUP); // Read current value.
|
||||
setupRegisterData &= 0xFC; // Erase the old value;
|
||||
setupRegisterData |= (m_power & 0x3);
|
||||
setRegister (RF_SETUP, setupRegisterData); // Write the new value.
|
||||
}
|
||||
|
||||
uint8_t
|
||||
NRF24L01::setSpeedRate (speed_rate_t rate) {
|
||||
uint8_t setupRegisterData = 0;
|
||||
|
||||
setupRegisterData = getRegister (RF_SETUP); // Read current value.
|
||||
setupRegisterData &= ~((1 << RF_DR_LOW) | (1 << RF_DR_HIGH));
|
||||
|
||||
switch (rate) {
|
||||
case NRF_250KBPS:
|
||||
setupRegisterData |= (1 << RF_DR_LOW) ;
|
||||
break;
|
||||
case NRF_1MBPS:
|
||||
break;
|
||||
case NRF_2MBPS:
|
||||
setupRegisterData |= (1 << RF_DR_HIGH);
|
||||
break;
|
||||
}
|
||||
|
||||
setRegister (RF_SETUP, setupRegisterData); // Write the new value.
|
||||
|
||||
if (setupRegisterData == getRegister (RF_SETUP)) {
|
||||
return 0x0;
|
||||
}
|
||||
|
||||
return 0x1;
|
||||
}
|
||||
|
||||
mraa_result_t
|
||||
NRF24l01::nrfCEHigh () {
|
||||
NRF24L01::ceHigh () {
|
||||
return mraa_gpio_write (m_cePinCtx, HIGH);
|
||||
}
|
||||
|
||||
mraa_result_t
|
||||
NRF24l01::nrfCELow () {
|
||||
NRF24L01::ceLow () {
|
||||
return mraa_gpio_write (m_cePinCtx, LOW);
|
||||
}
|
||||
|
||||
mraa_result_t
|
||||
NRF24l01::nrfCSOn () {
|
||||
NRF24L01::csOn () {
|
||||
return mraa_gpio_write (m_csnPinCtx, LOW);
|
||||
}
|
||||
|
||||
mraa_result_t
|
||||
NRF24l01::nrfCSOff () {
|
||||
NRF24L01::csOff () {
|
||||
return mraa_gpio_write (m_csnPinCtx, HIGH);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24l01::nrfListenForChannel() {
|
||||
if(!nrfIsSending() && nrfDataReady()) {
|
||||
nrfGetData(m_rxBuffer);
|
||||
dataRecievedHandler(); /* let know that data arrived */
|
||||
NRF24L01::pollListener() {
|
||||
if (dataReady()) {
|
||||
getData (m_rxBuffer);
|
||||
dataRecievedHandler (); /* let know that data arrived */
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::txFlushBuffer () {
|
||||
sendCommand (FLUSH_TX);
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setBeaconingMode () {
|
||||
setRegister (CONFIG, 0x12); // on, no crc, int on RX/TX done
|
||||
setRegister (EN_AA, 0x00); // no auto-acknowledge
|
||||
setRegister (EN_RXADDR, 0x00); // no RX
|
||||
setRegister (SETUP_AW, 0x02); // 5-byte address
|
||||
setRegister (SETUP_RETR, 0x00); // no auto-retransmit
|
||||
setRegister (RF_SETUP, 0x06); // 1MBps at 0dBm
|
||||
setRegister (STATUS, 0x3E); // clear various flags
|
||||
setRegister (DYNPD, 0x00); // no dynamic payloads
|
||||
setRegister (FEATURE, 0x00); // no features
|
||||
setRegister (RX_PW_P0, 32); // always RX 32 bytes
|
||||
setRegister (EN_RXADDR, 0x01); // RX on pipe 0
|
||||
|
||||
uint8_t addr[4] = { swapbits(0x8E), swapbits(0x89), swapbits(0xBE), swapbits(0xD6)};
|
||||
writeRegister (TX_ADDR, addr, 4);
|
||||
writeRegister (RX_ADDR_P0, addr, 4);
|
||||
|
||||
uint8_t index = 0;
|
||||
m_bleBuffer[index++] = 0x42; // PDU type, given address is random
|
||||
m_bleBuffer[index++] = 0x1B; // 6+3+2+16 = 27 bytes of payload
|
||||
|
||||
m_bleBuffer[index++] = BLE_MAC_0;
|
||||
m_bleBuffer[index++] = BLE_MAC_1;
|
||||
m_bleBuffer[index++] = BLE_MAC_2;
|
||||
m_bleBuffer[index++] = BLE_MAC_3;
|
||||
m_bleBuffer[index++] = BLE_MAC_4;
|
||||
m_bleBuffer[index++] = BLE_MAC_5;
|
||||
|
||||
m_bleBuffer[index++] = 2; // flags (LE-only, limited discovery mode)
|
||||
m_bleBuffer[index++] = 0x01;
|
||||
m_bleBuffer[index++] = 0x05;
|
||||
|
||||
m_bleBuffer[index++] = 17;
|
||||
m_bleBuffer[index++] = 0x08;
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::sendBeaconingMsg (uint8_t * msg) {
|
||||
const uint8_t chRf[] = {2, 26,80};
|
||||
const uint8_t chLe[] = {37,38,39};
|
||||
uint8_t index = BLE_PAYLOAD_OFFSET + 16;
|
||||
|
||||
memcpy (&m_bleBuffer[BLE_PAYLOAD_OFFSET], msg, 16);
|
||||
m_bleBuffer[index++] = 0x55;
|
||||
m_bleBuffer[index++] = 0x55;
|
||||
m_bleBuffer[index++] = 0x55;
|
||||
|
||||
uint8_t channel = 0;
|
||||
while (++channel != sizeof(chRf)) {
|
||||
setRegister (RF_CH, chRf[channel]);
|
||||
setRegister (STATUS, 0x6E); //clear flags
|
||||
|
||||
blePacketEncode (m_bleBuffer, index, chLe[channel]);
|
||||
|
||||
sendCommand (FLUSH_TX); // Clear RX Fifo
|
||||
sendCommand (FLUSH_RX); // Clear TX Fifo
|
||||
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, W_TX_PAYLOAD); // Write cmd to write payload
|
||||
writeBytes (m_bleBuffer, NULL, 32); // Write payload
|
||||
csOff ();
|
||||
|
||||
setRegister (CONFIG, 0x12); // tx on
|
||||
ceHigh (); // Start transmission
|
||||
usleep (10000);
|
||||
ceLow ();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* ---------------
|
||||
* PRIVATE SECTION
|
||||
* ---------------
|
||||
*/
|
||||
|
||||
void
|
||||
NRF24L01::writeBytes (uint8_t * dataout, uint8_t * datain, uint8_t len) {
|
||||
for (uint8_t i = 0; i < len; i++) {
|
||||
if (datain != NULL) {
|
||||
datain[i] = mraa_spi_write (m_spi, dataout[i]);
|
||||
} else {
|
||||
mraa_spi_write (m_spi, dataout[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::setRegister (uint8_t reg, uint8_t value) {
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
|
||||
mraa_spi_write (m_spi, value);
|
||||
csOff ();
|
||||
}
|
||||
|
||||
uint8_t
|
||||
NRF24L01::getRegister (uint8_t reg) {
|
||||
uint8_t data = 0;
|
||||
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, R_REGISTER | (REGISTER_MASK & reg));
|
||||
data = mraa_spi_write (m_spi, data);
|
||||
csOff ();
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::readRegister (uint8_t reg, uint8_t * value, uint8_t len) {
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, R_REGISTER | (REGISTER_MASK & reg));
|
||||
writeBytes (value, value, len);
|
||||
csOff ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::writeRegister (uint8_t reg, uint8_t * value, uint8_t len) {
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, W_REGISTER | (REGISTER_MASK & reg));
|
||||
writeBytes (value, NULL, len);
|
||||
csOff ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::sendCommand (uint8_t cmd) {
|
||||
csOn ();
|
||||
mraa_spi_write (m_spi, cmd);
|
||||
csOff ();
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::bleCrc (const uint8_t* data, uint8_t len, uint8_t* dst) {
|
||||
uint8_t v, t, d;
|
||||
while(len--) {
|
||||
d = *data++;
|
||||
for(v = 0; v < 8; v++, d >>= 1){
|
||||
t = dst[0] >> 7;
|
||||
dst[0] <<= 1;
|
||||
if(dst[1] & 0x80) dst[0] |= 1;
|
||||
dst[1] <<= 1;
|
||||
if(dst[2] & 0x80) dst[1] |= 1;
|
||||
dst[2] <<= 1;
|
||||
|
||||
if(t != (d & 1)) {
|
||||
dst[2] ^= 0x5B;
|
||||
dst[1] ^= 0x06;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::bleWhiten (uint8_t* data, uint8_t len, uint8_t whitenCoeff) {
|
||||
uint8_t m;
|
||||
while(len--) {
|
||||
for(m = 1; m; m <<= 1) {
|
||||
if(whitenCoeff & 0x80){
|
||||
whitenCoeff ^= 0x11;
|
||||
(*data) ^= m;
|
||||
}
|
||||
whitenCoeff <<= 1;
|
||||
}
|
||||
data++;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
NRF24L01::blePacketEncode(uint8_t* packet, uint8_t len, uint8_t chan) {
|
||||
//length is of packet, including crc. pre-populate crc in packet with initial crc value!
|
||||
uint8_t i, dataLen = len - 3;
|
||||
|
||||
bleCrc(packet, dataLen, packet + dataLen);
|
||||
for(i = 0; i < 3; i++, dataLen++) {
|
||||
packet[dataLen] = swapbits(packet[dataLen]);
|
||||
}
|
||||
|
||||
bleWhiten(packet, len, (swapbits(chan) | 2));
|
||||
for(i = 0; i < len; i++) {
|
||||
packet[i] = swapbits(packet[i]);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t
|
||||
NRF24L01::swapbits(uint8_t a) {
|
||||
uint8_t v = 0;
|
||||
|
||||
if(a & 0x80) v |= 0x01;
|
||||
if(a & 0x40) v |= 0x02;
|
||||
if(a & 0x20) v |= 0x04;
|
||||
if(a & 0x10) v |= 0x08;
|
||||
if(a & 0x08) v |= 0x10;
|
||||
if(a & 0x04) v |= 0x20;
|
||||
if(a & 0x02) v |= 0x40;
|
||||
if(a & 0x01) v |= 0x80;
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user