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302 lines
11 KiB
C
302 lines
11 KiB
C
/*
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* Author: Jon Trulson <jtrulson@ics.com>
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* Copyright (c) 2017 Intel Corporation.
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*
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* The MIT License
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LSM303D_DEFAULT_I2C_BUS 0
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#define LSM303D_DEFAULT_I2C_ADDR 0x1e
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// from the WHO_AM_I_* register
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#define LSM303D_CHIPID 0x49
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// Due to the fact that this chip is currently obsolete, we only
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// support minimum functionality. This register map is not
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// complete. While all registers are specified, bitfields and
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// enumerants are only specified for certain registers of
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// interest. Feel free to add what you need.
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// NOTE: Reserved registers must not be written into or permanent
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// damage to the device can result. Reading from them may return
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// indeterminate values. Registers containing reserved bitfields
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// must be written as 0.
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/**
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* LSM303D registers
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*/
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typedef enum {
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// 0x00-0x04 reserved
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LSM303D_REG_TEMP_OUT_L = 0x05,
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LSM303D_REG_TEMP_OUT_H = 0x06,
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LSM303D_REG_STATUS_M = 0x07,
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LSM303D_REG_OUT_X_L_M = 0x08,
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LSM303D_REG_OUT_X_H_M = 0x09,
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LSM303D_REG_OUT_Y_L_M = 0x0a,
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LSM303D_REG_OUT_Y_H_M = 0x0b,
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LSM303D_REG_OUT_Z_L_M = 0x0c,
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LSM303D_REG_OUT_Z_H_M = 0x0d,
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// 0x0e reserved
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LSM303D_REG_WHO_AM_I = 0x0f,
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// 0x10-0x11 reserved
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LSM303D_REG_INT_CTRL_M = 0x12,
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LSM303D_REG_INT_SRC_M = 0x13,
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LSM303D_REG_INT_THS_L_M = 0x14,
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LSM303D_REG_INT_THS_H_M = 0x15,
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LSM303D_REG_OFFSET_X_L_M = 0x16,
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LSM303D_REG_OFFSET_X_H_M = 0x17,
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LSM303D_REG_OFFSET_Y_L_M = 0x18,
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LSM303D_REG_OFFSET_Y_H_M = 0x19,
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LSM303D_REG_OFFSET_Z_L_M = 0x1a,
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LSM303D_REG_OFFSET_Z_H_M = 0x1b,
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LSM303D_REG_REFERENCE_X = 0x1c,
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LSM303D_REG_REFERENCE_Y = 0x1d,
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LSM303D_REG_REFERENCE_Z = 0x1e,
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LSM303D_REG_CTRL0 = 0x1f,
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LSM303D_REG_CTRL1 = 0x20,
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LSM303D_REG_CTRL2 = 0x21,
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LSM303D_REG_CTRL3 = 0x22,
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LSM303D_REG_CTRL4 = 0x23,
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LSM303D_REG_CTRL5 = 0x24,
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LSM303D_REG_CTRL6 = 0x25,
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LSM303D_REG_CTRL7 = 0x26,
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LSM303D_REG_STATUS_A = 0x27,
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LSM303D_REG_OUT_X_L_A = 0x28,
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LSM303D_REG_OUT_X_H_A = 0x29,
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LSM303D_REG_OUT_Y_L_A = 0x2a,
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LSM303D_REG_OUT_Y_H_A = 0x2b,
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LSM303D_REG_OUT_Z_L_A = 0x2c,
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LSM303D_REG_OUT_Z_H_A = 0x2d,
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LSM303D_REG_FIFO_CTRL = 0x2e,
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LSM303D_REG_FIFO_SRC = 0x2f,
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LSM303D_REG_IG_CFG1 = 0x30,
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LSM303D_REG_IG_SRC1 = 0x31,
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LSM303D_REG_IG_THS1 = 0x32,
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LSM303D_REG_IG_DUR1 = 0x33,
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LSM303D_REG_IG_CFG2 = 0x34,
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LSM303D_REG_IG_SRC2 = 0x35,
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LSM303D_REG_IG_THS2 = 0x36,
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LSM303D_REG_IG_DUR2 = 0x37,
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LSM303D_REG_CLICK_CFG = 0x38,
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LSM303D_REG_CLICK_SRC = 0x39,
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LSM303D_REG_CLICK_THS = 0x3a,
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LSM303D_REG_TIME_LIMIT = 0x3b,
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LSM303D_REG_TIME_LATENCY = 0x3c,
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LSM303D_REG_TIME_WINDOW = 0x3d,
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LSM303D_REG_ACT_THS = 0x3e,
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LSM303D_REG_ACT_DUR = 0x3f,
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} LSM303D_REGS_T;
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// Accelerometer registers
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/**
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* CTRL1 bits
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*/
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typedef enum {
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LSM303D_CTRL1_AXEN = 0x01, // axis enables
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LSM303D_CTRL1_AYEN = 0x02,
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LSM303D_CTRL1_AZEN = 0x04,
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LSM303D_CTRL1_BDU = 0x08,
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LSM303D_CTRL1_AODR0 = 0x10,
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LSM303D_CTRL1_AODR1 = 0x20,
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LSM303D_CTRL1_AODR2 = 0x40,
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LSM303D_CTRL1_AODR3 = 0x80,
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_LSM303D_CTRL1_AODR_MASK = 15,
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_LSM303D_CTRL1_AODR_SHIFT = 4,
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} LSM303D_CTRL1_BITS_T;
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/**
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* CTRL1_AODR values (and power mode)
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*/
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typedef enum {
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LSM303D_AODR_POWER_DOWN = 0,
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LSM303D_AODR_3_125HZ = 1, // 3.125Hz
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LSM303D_AODR_6_25HZ = 2,
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LSM303D_AODR_12_5HZ = 3,
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LSM303D_AODR_25HZ = 4,
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LSM303D_AODR_50HZ = 5,
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LSM303D_AODR_100HZ = 6,
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LSM303D_AODR_200HZ = 7,
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LSM303D_AODR_400HZ = 8,
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LSM303D_AODR_800HZ = 9,
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LSM303D_AODR_1600HZ = 10,
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} LSM303D_AODR_T;
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/**
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* CTRL2 bits
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*/
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typedef enum {
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LSM303D_CTRL2_SIM = 0x01,
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LSM303D_CTRL2_AST = 0x02,
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// 0x04 reserved
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LSM303D_CTRL2_AFS0 = 0x08, // full scale
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LSM303D_CTRL2_AFS1 = 0x10,
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LSM303D_CTRL2_AFS2 = 0x20,
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_LSM303D_CTRL2_AFS_MASK = 7,
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_LSM303D_CTRL2_AFS_SHIFT = 3,
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LSM303D_CTRL2_ABW0 = 0x40,
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LSM303D_CTRL2_ABW1 = 0x80,
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_LSM303D_CTRL2_ABW_MASK = 3,
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_LSM303D_CTRL2_ABW_SHIFT = 6,
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} LSM303D_CTRL2_BITS_T;
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/**
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* CTRL2_AFS values (full scale)
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*/
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typedef enum {
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LSM303D_AFS_2G = 0, // 2G
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LSM303D_AFS_4G = 1,
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LSM303D_AFS_6G = 2,
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LSM303D_AFS_8G = 3,
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LSM303D_AFS_16G = 4,
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} LSM303D_AFS_T;
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/**
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* CTRL5 bits
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*/
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typedef enum {
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LSM303D_CTRL5_LIR1 = 0x01,
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LSM303D_CTRL5_LIR2 = 0x02,
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LSM303D_CTRL5_MODR0 = 0x04, // mag odr
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LSM303D_CTRL5_MODR1 = 0x08,
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LSM303D_CTRL5_MODR2 = 0x10,
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_LSM303D_CTRL5_MODR_MASK = 7,
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_LSM303D_CTRL5_MODR_SHIFT = 2,
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LSM303D_CTRL5_M_RES0 = 0x20, // resolution
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LSM303D_CTRL5_M_RES1 = 0x40,
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_LSM303D_CTRL5_MRES_MASK = 3,
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_LSM303D_CTRL5_MRES_SHIFT = 6,
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LSM303D_CTRL5_TEMP_EN = 0x80,
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} LSM303D_CTRL5_BITS_T;
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/**
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* CTRL5_MODR values (mag output data rate)
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*/
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typedef enum {
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LSM303D_MODR_3_125HZ = 0, // 3.125Hz
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LSM303D_MODR_6_25HZ = 1,
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LSM303D_MODR_12_5HZ = 2,
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LSM303D_MODR_25HZ = 3,
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LSM303D_MODR_50HZ = 4,
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LSM303D_MODR_100HZ = 5,
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} LSM303D_MODR_T;
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/**
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* CTRL5_M_RES values (resolution)
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*/
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typedef enum {
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LSM303D_M_RES_LOW = 0,
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LSM303D_M_RES_HIGH = 3,
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} LSM303D_M_RES_T;
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/**
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* CTRL6 bits
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*/
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typedef enum {
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// 0x01-0x10 reserved
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LSM303D_CTRL6_MFS0 = 0x20,
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LSM303D_CTRL6_MFS1 = 0x40,
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_LSM303D_CTRL6_MFS_MASK = 3,
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_LSM303D_CTRL6_MFS_SHIFT = 5,
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// 0x80 reserved
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} LSM303D_CTRL6_BITS_T;
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/**
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* CTRL6_MFS values (mag full scale)
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*/
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typedef enum {
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LSM303D_MFS_2 = 0, // 2 Gauss
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LSM303D_MFS_4 = 1,
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LSM303D_MFS_8 = 2,
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LSM303D_MFS_12 = 3,
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} LSM303D_MFS_T;
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/**
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* CTRL7 bits
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*/
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typedef enum {
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LSM303D_CTRL7_MD0 = 0x01,
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LSM303D_CTRL7_MD1 = 0x02,
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_LSM303D_CTRL7_MD_MASK = 3,
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_LSM303D_CTRL7_MD_SHIFT = 0,
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LSM303D_CTRL7_MLP = 0x04,
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// 0x08 reserved
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LSM303D_CTRL7_T_ONLY = 0x10,
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LSM303D_CTRL7_AFDS = 0x20,
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LSM303D_CTRL7_AHPM0 = 0x40,
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LSM303D_CTRL7_AHPM1 = 0x80,
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_LSM303D_CTRL7_AHPM_MASK = 3,
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_LSM303D_CTRL7_AHPM_SHIFT = 6,
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} LSM303D_CTRL7_BITS_T;
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/**
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* CTRL7_MD values (power mode)
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*/
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typedef enum {
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LSM303D_MD_CONTINUOUS = 0,
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LSM303D_MD_SINGLE = 1,
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LSM303D_MD_POWER_DOWN = 3, // 2 is pwr down too
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} LSM303D_MD_T;
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#ifdef __cplusplus
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}
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#endif
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