#include "avr/io.h"
#include "avr/sleep.h"
#include "avr/fuse.h"
#include "avr/interrupt.h"
#include "util/delay.h"

#define ZH_NRF24_CE_DDR DDRB
#define ZH_NRF24_CE_PORT PORTB
#define ZH_NRF24_CE_PIN PORTB2
#define ZH_NRF24_CSN_DDR DDRB
#define ZH_NRF24_CSN_PORT PORTB
#define ZH_NRF24_CSN_PIN PORTB1

FUSES = {0xE2, 0xDF, 0x07};

#define GATEWAY_CHANNEL 120

#define DEVICE_ID 50
#define DEVICE_TYPE 4

#define NRF24_CE_HIGH (ZH_NRF24_CE_PORT |= (1 << ZH_NRF24_CE_PIN))
#define NRF24_CE_LOW (ZH_NRF24_CE_PORT &= ~(1 << ZH_NRF24_CE_PIN))
#define NRF24_SPI_START (ZH_NRF24_CSN_PORT &= ~(1 << ZH_NRF24_CSN_PIN))
#define NRF24_SPI_STOP (ZH_NRF24_CSN_PORT |= (1 << ZH_NRF24_CSN_PIN))

static void zh_pad_interrupt_init(void);
static void zh_spi_init(void);
static uint8_t zh_spi_transfer(uint8_t data);
static void zh_nrf24_init(void);
static void zh_nrf24_send(uint8_t *buf, uint8_t size);
static uint8_t zh_nrf24_write_buffer(uint8_t cmd, uint8_t *buf, uint8_t count);
static uint8_t zh_nrf24_write_register(uint8_t reg, uint8_t val);
static uint8_t zh_nrf24_write_buff_register(uint8_t reg, uint8_t *buf, uint8_t count);
static uint8_t zh_nrf24_send_command(uint8_t cmd);
static float zh_get_battery_level_charge(void);

static uint64_t gateway_address = 0xDDEEFF;
static int16_t transmitted_data[7] = {DEVICE_ID, DEVICE_TYPE, 0x00, 0x00, 0x00, 0x00, 0x00};

int main(void)
{
	cli();
	zh_pad_interrupt_init();
	zh_spi_init();
	zh_nrf24_init();
	// set_sleep_mode(SLEEP_MODE_PWR_DOWN);
	// sleep_enable();
	sei();
	for (;;)
	{
		transmitted_data[2] = (zh_get_battery_level_charge() * 100);
		zh_nrf24_send((uint8_t *)&transmitted_data, sizeof(transmitted_data));
		// sleep_cpu();
		_delay_ms(5000);
	}
	return 0;
}

ISR(INT1_vect)
{
	cli();
	transmitted_data[2] = (zh_get_battery_level_charge() * 100);
	zh_nrf24_send((uint8_t *)&transmitted_data, sizeof(transmitted_data));
	sei();
}

static void zh_pad_interrupt_init(void)
{
	EICRA |= ((1 << ISC11) | (1 << ISC10));
	EIMSK |= (1 << INT1);
}

static void zh_spi_init(void)
{
	DDRB |= ((1 << PORTB2) | (1 << PORTB3) | (1 << PORTB5));
	SPCR |= ((1 << SPE) | (1 << MSTR));
}

static uint8_t zh_spi_transfer(uint8_t data)
{
	SPDR = data;
	while ((SPSR & (1 << SPIF)) == 0)
	{
	}
	return SPDR;
}

static void zh_nrf24_init(void)
{
	ZH_NRF24_CE_DDR |= (1 << ZH_NRF24_CE_PIN);
	ZH_NRF24_CSN_DDR |= (1 << ZH_NRF24_CSN_PIN);
	zh_nrf24_write_register(0x00, 0x48);
	zh_nrf24_write_register(0x01, 0x01);
	zh_nrf24_write_register(0x02, 0x01);
	zh_nrf24_write_register(0x03, 0x01);
	zh_nrf24_write_register(0x04, 0xFF);
	zh_nrf24_write_register(0x05, GATEWAY_CHANNEL);
	zh_nrf24_write_register(0x06, 0x26);
	zh_nrf24_write_buff_register(0x0A, (uint8_t *)&gateway_address, 3);
	zh_nrf24_write_buff_register(0x10, (uint8_t *)&gateway_address, 3);
}

static void zh_nrf24_send(uint8_t *buf, uint8_t size)
{
	zh_nrf24_write_register(0x00, 0x4A);
	_delay_ms(2);
	zh_nrf24_write_buffer(0xA0, buf, size);
	NRF24_CE_HIGH;
	_delay_us(15);
	NRF24_CE_LOW;
	while ((zh_nrf24_send_command(0xFF) & 0x30) == 0)
	{
		_delay_ms(1);
	}
	zh_nrf24_write_register(0x07, zh_nrf24_send_command(0xFF));
	zh_nrf24_send_command(0xE1);
	zh_nrf24_write_register(0x00, 0x48);
}

static uint8_t zh_nrf24_write_buffer(uint8_t cmd, uint8_t *buf, uint8_t count)
{
	NRF24_SPI_START;
	uint8_t status = zh_spi_transfer(cmd);
	while (count-- != 0)
	{
		zh_spi_transfer(*(buf++));
	}
	NRF24_SPI_STOP;
	return status;
}

static uint8_t zh_nrf24_write_register(uint8_t reg, uint8_t val)
{
	NRF24_SPI_START;
	uint8_t status = zh_spi_transfer(reg | 0x20);
	zh_spi_transfer(val);
	NRF24_SPI_STOP;
	return status;
}

static uint8_t zh_nrf24_write_buff_register(uint8_t reg, uint8_t *buf, uint8_t count)
{
	return zh_nrf24_write_buffer((reg | 0x20), buf, count);
}

static uint8_t zh_nrf24_send_command(uint8_t cmd)
{
	NRF24_SPI_START;
	uint8_t status = zh_spi_transfer(cmd);
	NRF24_SPI_STOP;
	return status;
}

static float zh_get_battery_level_charge(void)
{
	ADMUX = ((1 << REFS0) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1));
	ADCSRA |= (1 << ADEN);
	_delay_ms(10);
	ADCSRA |= (1 << ADSC);
	while ((ADCSRA & (1 << ADSC)) != 0)
	{
	}
	ADCSRA &= ~(1 << ADEN);
	return ((1024 * 1.1) / (ADCL + (ADCH * 256)));
}